SSTL_3, V, defined in EIA/JESD ; SSTL_2, V, defined in EIA/ JESDB used in DDR among other things. SSTL_18, V, defined in. STUB SERIES TERMINATED. LOGIC FOR VOLTS (SSTL_2). EIA/JESD SEPTEMBER ELECTRONIC INDUSTRIES ALLIANCE. JEDEC Solid State . SSTL (JESD, JESDB, JESD). • HSTL (JESD). LVTTL and LVCMOS were developed as a direct result of technology scaling. With each reduction in.

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Figure 3 shows the typical dc environment that the output buffer is presented with. No claims to be in conformance with this standard may jrsd8 made unless all requirements stated in the standard are met. This is accomplished precisely because drivers and receivers are specified independently of each other.

Almost representatives, appointed by some JEDEC member companies jed8 together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike. NOTE 2 A 1. This is illustrated in figure 2. One advantage of this approach is that there is no need for a VTT power supply.

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Typically the value of VREF is expected to be 0. Units V mV Notes 1 1 0. The output specifications are divided into two classes, Class I and Class II, which are distinguished by drive requirements and application.

Making this distinction jrsd8 important for the design of high gain, differential, receivers that are required. This can be expressed by equation-1 or equation The driver specification now must guarantee that these values of VIN are obtained in the worst case conditions specified by this standard.

Units V V Notes 2. Busses may be terminated by resistors to an external termination voltage. Clearly it is not the intention jsd8 show all possible variations in this standard. The standard defines a reference voltage VREF which is used at the receivers as well as a voltage VTT to which termination resistors are connected. Compliant devices must meet the VSwing ac specification under actual use conditions. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.


In order to meet the mV minimum requirement for VIN, a minimum of 8. In this example a Class II type buffer might be preferred since it comes closer, in conjunction with the series resistor, to match the characteristic impedance of the transmission line. Note however, that all timing specifications are still set relative to the ac input level.

Stub Series Terminated Logic – Wikipedia

F or info rm ationcon tact: The tester may therefore supply signals with a 1. However, the drivers are connected directly onto the bus so there are no stubs present.

However a Class II buffer would dissipate more power jeed8 to its larger current drive and thus might require special cooling. Under these conditions VOH is 1.

An example is shown in jdsd8 7. If the driver outputs are sized for this condition, then for all other VDDQ voltage applications, the resulting input signal will be larger than the minimum mV.

The test circuit is assumed to be similar to the circuit shown in figure jesr8. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments.

NOTE 4 AC test conditions may be measured under nominal voltage conditions as long as jsd8 supplier can demonstrate by analysis that the device will meet its timing specifications under all supported voltage conditions. See also figure 2. An example of this is shown in figure 6. Vx ac indicates the voltage at which differential input signals must be crossing. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint.


AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis, that the device will meet its timing specifications under all supported voltage conditions. In this non binding section jeed8 will show some derived applications.

The ac values are chosen to indicate the levels at which the receiver must meet its timing specifications.

Jssd8 second clause defines the minimum dc and ac input parametric requirements and ac test conditions for inputs on compliant devices. The Standards, Publications, and Outlines that they generate are accepted throughout the world.

The system designer will be able to vary impedance levels, termination resistors and supply voltage and be able to calculate the effect on system voltage margins. In that case, the jessd8 may decide to eliminate the series resistors entirely. An example of this may be address drivers on a memory board.

Jeed8 relationship of the different levels is shown in figure 1. The test circuit is assumed to be similar to the circuit shown in figure 4. By downloading this file the individual agrees not to charge for or resell the resulting material.

Stub Series Terminated Logic

The system designer can be sure that the device will switch state a certain amount of time after the input has crossed ac threshold and not switch back as long as jesf8 input stays beyond the dc threshold. With a series resistor of 25? External resistors provide this isolation and also reduce the on-chip power dissipation of the drivers. An example of ringing is illustrated in the dotted wave-form.

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